As the operation speed of computer systems continues to increase, the need exists to delay either clock or data signals to optimize the critical timing within the computer system due to the timing requirements of system components. Also as the clock rate in the system increases, the timing between the computer elements and within the computer chips becomes critical.
However, a delay line used in these systems should have “noise free” operation, which can be affected by two key characteristics: (1) delay programming; and (2) power supply noise in delay generation. The conventional method of using logic gates as delay elements and using multiplexers to switch between these elements suffers from glitch and delay variation due to power supply noise.
FIG. 1 illustrates a conventional way of building a programmable delay line using a multiplexer. As shown in delay line architecture 100, an input signal A is passed through serial delay elements 102-1, 102-2, and 102-3. The original input signal and the outputs of the three delay elements serve as inputs to multiplexer 104. Signal S is used to select which one of the original signal and the outputs of the three delay elements serves as output signal Z.
However, since multiplexers are not normally glitch free when they selectively switch from one input to the other, the output of the delay scheme will have a glitch added to the output signal.
The constant unit delay is an important consideration particularly when deskewing data, since any variation in delay decreases overall performance. Conventional delay circuits with logic gate unit delays are typically varied by power supply noise.
FIG. 2 shows a conventional delay element using an inverter structure. That is, the delay element in FIG. 2 can serve as one or more of the delay elements (102-1, 102-2, 102-3) in architecture 100 of FIG. 1. As is well known in signal processing art, complementary field effect transistors (FETs) T1 and T2 serve as a first inverting stage, and complementary FETs T3 and T4 serve as a second inverting stage. Also, as per convention, a FET with a circle on the gate terminal is known to be a positive-type FET or pFET, while a FET without a circle on the gate terminal is a negative-type FET or nFET. Also, typical conventions regarding source and drain terminals are employed here.
Typically, the time it takes for input signal A to propagate through the two inverting stages and appear as output signal Z is considered the delay attributable to the delay element.
The following U.S. patents illustrate limitations of conventional “noise free” operation in programmable delay lines: U.S. Pat. No. 6,421,784; U.S. Pat. No. 6,285,229; U.S. Pat. No. 6,546,530; U.S. Pat. No. 6,708,238; U.S. Pat. No. 5,374,860; U.S. Pat. No. 5,670,904; U.S. Pat. No. 6,611,936; U.S. Pat. No. 6,255,879; U.S. Pat. No. 6,014,050; U.S. Pat. No. 6,144,786 and U.S. Pat. No. 6,400,735.
Nonetheless, a need exists for a delay element for computer systems that has glitchless operation, which overcomes the above and other drawbacks, as well as improving over conventional glitchless delay line approaches.